Overview
This two day workshop describes the fundamentals of manufacturing test and the use of TetraMAX®--the Synopsys ATPG Tool for SOC design. Through a combination of classroom lecture and hands-on labs, you will learn how to:

• Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
• Describe the test protocol and test pattern timing using STIL
• Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
• Troubleshoot fault-coverage problems
• Save and validate test patterns
• Troubleshoot simulation failures
• Diagnose failures on the ATE

• Incorporate TetraMAX® ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count, and ATPG run-time for a full-scan or almost full-scan design
• Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, DFT Compiler, or from scratch
• Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
• Understand how to use at least three options to increase test coverage and/or decrease the number of required test patterns
• Save test patterns in a proper format for simulation and transfer to an ATE
• Validate test patterns using Verilog Direct Pattern Validation or MAX Testbench
• Use TetraMAX diagnosis features to analyze failures on the ATE

Audience Profile
ASIC, SoC or Test Engineers who perform ATPG at the Chip or SoC level

Prerequisites
To benefit the most from the material presented in this workshop, students should have completed the DFT Compiler 1 workshop or possess equivalent knowledge with DFT Compiler and fundamentals of manufacturing test including:

• Understanding the differences between manufacturing and design verification testing
• Stuck-at fault model
• Internal and boundary scan chains
• Scan shift and capture violations
• Major scan design-for-test rules concerning flip-flops, latches and bi-directional/tri-state drivers
• Tradeoffs between having single or multiple
• Understanding of digital IC logic design
• Working knowledge of Verilog or VHDL language
• Familiarity with UNIX workstations running X-windows
• Familiarity with vi, emacs, or other UNIX text editors

• Introduction to ATPG Test
• Building ATPG Models
• Running DRC
• Controlling ATPG

• Minimizing ATPG Patterns
• Writing ATPG Patterns
• Pattern Validation
• Diagnosis
• Conclusion

• TetraMAX 2008.09-SP4
• VCS 2008.12-4