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PrimeTime: Debugging Constraints
OVERVIEW
This workshop addresses the most time-consuming part of static timing
analysis: debugging constraints. The workshop provides a method to identify
potential timing problems, identify the cause, and determine the effects
of these problems. Armed with this information, students will now be
able to confirm that constraints are correct or, if incorrect, will
have sufficient information to correct the problem.
Incorrect STA constraints must be identified because they obscure real
timing violations and can cause two problems: either the real violations
are missed and not reported or violations are reported that are not
real, making it difficult to find the real violations hidden among them.
Following are three examples among many that students should be able
to debug and resolve at the end of this workshop:
- Identify the specific registers in a design that are expecting
but not receiving a clock, then determine a potential clock source
for creating the missing clock. .
- An output port has been constrained but is not being exercised by
PrimeTime because all timing paths to this port are broken. Identify
where and why the paths have been broken in order to verify if the
STA results will be correct and complete.
- Identify combinational loops in the design. Determine if the timing
arc that is disabled automatically by PrimeTime breaks any valid timing
paths, thus requiring dynamic loop breaking to be used during STA.
Skills learned include:
- Identifying constraint problems using three key PrimeTime commands:
check_timing; report_analysis_coverage; report_timing.
- Pinpointing the cause and determining the effects of constraint
warnings through mastery of eight PrimeTime commands and a custom
Tcl procedure: all_fanin; all_fanout; get_attribute; report_disable_timing;
report_lib; report_cell; report_port; report_clock; report_case_propagation.
Hands-on labs follow each training module, allowing students to apply
the knowledge learned during the lecture to debug STA problems on a complex,
unfamiliar design. Upon completion of the labs, students should have mastered
constraint debugging skills that are essential when performing advanced
analysis and debugging on any netlist.
This workshop is part of the Synopsys Designers' Edge Series targeted
at the advanced user, who is facing difficult design challenges and wants
to maximize productivity with Synopsys tools. These workshops include
the most up-to-date tool and methodology information available.
This workshop is also offered as part of the Synopsys Virtual
Classroom: PrimeTime: Debugging Constraints
.
Please Note: This class was formerly
delivered as: PrimeTime: Advanced STA Constraint Debugging.
OBJECTIVES
At the end of this workshop the student should be able to:
- Pinpoint the cause and determine the effects of check_timing and
report_analysis_coverage warnings
- Execute seven PrimeTime commands and two custom procedures to trace
from the warning to the cause and explore objects in that path
- Systematically debug scripts to eliminate obvious problems using
PrimeTime
- Independently and fully utilize check_timing and
report_analysis_coverage to flag remaining constraint problems
- Identify key pieces of a timing report for debugging final
constraint problems
AUDIENCE PROFILE
Design or Verification engineers who perform STA using PrimeTime.
PREREQUISITES
To benefit the most from the material presented in this workshop, you
should:
- Have taken PrimeTime 1
OR
- Possess equivalent knowledge with PrimeTime including:
- Script writing using Tcl
- Reading and linking a design
- Writing block constraints
- Generating and interpreting timing reports using report_timing and
report_constraint commands
COURSE OUTLINE
Unit 1: Tools of the Trade
- Lab 1 A Guided Tour of the Tools of the Trade
- Lab 2 Choose the Correct Command and Apply It
Unit 2:
Complete Qualification of PrimeTime Inputs
- Lab 3 Find and Debug Potential Constraint Problems
SYNOPSYS TOOLS USED
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