Overview
In this class you will perform high-level design steps necessary to synthesize, analyze, and verify a multi-voltage design with shutdown requirements using the IEEE P1801 UPF-based Synopsys Eclypse Low-Power Flow overview. You will:

• Identify the library requirements to implement a MV low-power design
• Create, modify, interpret, and apply power-intent (UPF 1.0) files
• Correctly specify PVT requirements for MV low-power optimizations
• Perform low-power RTL synthesis generating a MV-clean design
• Insert power-domain aware scan chains
• Identify low-power ATPG techniques to minimize power
• Conduct static timing analysis on the pre-layout design
• Analyze average and peak power consumptions
• Check for logic equivalence of RTL and gate-level designs
• Interpret the results of running a voltage-aware simulation
• Verify the results of running MV rule checks on the gate-level design

• Create, modify, interpret, and apply UPF files that capture the stated power intent of Multi-VDD designs with shutdown requirements
• Synthesize design for the required power intent and power-optimization requirements
• Insert scan chains to the synthesized design taking into account the existing power domains and special multi-voltage cells while minimizing switching activity
• Describe two techniques used to minimize power during ATPG
• Ensure that the gate-level design is MV clean
• Generate gate-level design netlist, constraints, and power-intent files for pre-layout verification and physical implementation
• Ensure equivalence checking of logic functionality between RTL and gate- level using the design and UPF files
• Run static timing analysis using instance-based linking
• Perform peak and average power analysis based on UPF power domain and power nets
• Verify design functionality using the results of a voltage-aware simulator
• Analyze the results of performing MV rule checking on gate-level design

Audience Profile
Logic design and/or verification engineers who have a need to implement, analyze, and verify designs requiring the lowest possible power consumption using the Synopsys Front-End Eclypse Low Power Flow. CAD Engineers and Managers responsible for Low Power flow will also find this workshop beneficial.

Prerequisites
To benefit the most from the material presented in this workshop, students need:

• A basic working knowledge of Synopsys Design Compiler and PrimeTime tools. Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete this workshop
• An awareness of the basics of low-power design techniques. This workshop teaches how to implement these techniques

• Synopsys Low Power Flow Overview
• Low Power Flow Infrastructure and UPF (Lab)
• RTL Synthesis for Low Power (Lab)
• Low Power DFT and ATPG (Lab)

• Logic Equivalence Checking (Lab)
• Static Timing and Power Analysis (Lab)
• Voltage aware simulation (Lab)
• Multi Voltage Rule Checking (Lab)

• Design Compiler - Topographical 2008.09-SP3
• Design Vision 2008.09-SP3
• DFT Compiler (with DFTMAX enabled) 2008.09-SP3
• Power Compiler 2008.09-SP3
• Formality 2008.09-SP3
• PrimeTime 2008.12-SP2
• PrimeTime-PX 2008.12-SP2
• nWave 2008.12-SP2
• VCS 2008.09
• MVTOOLS (MVSIM and MVRC) 2.3BR2.1