Overview
In this workshop, you create a layout, and verify a design using Multi-Voltage (MV) techniques to achieve the lowest practical operating power dissipation for the required performance using a complete suite of Synopsys tools. The flow consists of four major steps:

1) Specifying power intent using UPF
2) Verification (of functionality and Power intent)
3) Logical and Physical Implementation
4) Analysis (for Timing, Power, and Functionality)

Each step is MV-aware, based on the industry standard Unified Power Format (UPF):
You will start with the Multi-Vth, Multi-Voltage libraries with special cells and the design description consisting of RTL, UPF, SDC, and DEF files .In the verification step, you will use a voltage-aware simulator to validate the RTL design for the required power intent and functionality. You will then take the design through RTL synthesis (for dynamic, leakage, and MV optimizations) and power-domain-aware scan insertion. Next you will analyze the pre-layout netlist for timing requirements, power consumption, and logic equivalence. During the physical implementation step, consisting of floorplan, power plan, P&R, and CTS, you will build the required MTCMOS power gating (switch) network.

• Specify Power intent using the Unified Power Format (UPF)
• Ensure library requirement (PG pins, Special cells)
• Perform MV-aware simulation using your RTL and UPF specifications
• Perform MV-aware rule checks using your RTL and UPF
• Modify UPF and script files for the low power requirements
• Synthesize the design using low-Power techniques
• Insert Power-domain-aware scan chains
• Describe the steps for generating low-power ATPG
• Create a power-aware floorplan
• Synthesize multiple power grids with MTCMOS power switches
• Synthesize clock trees
• Place and route the design
• Conduct static timing analysis
• Perform average and peak power analysis
• Analyze and address dynamic IR-drop effects
• Verify logic equivalence of various design transformations
• Perform a sanity check using MV rule checking

Audience Profile
ASIC, back-end, or layout designers with experience in logic design, design verification, Place&Route, or signoff verification. CAD engineers responsible for flow development will also find this very beneficial.

Prerequisites
To benefit the most from the material presented in this workshop, students should:

• Have a basic working knowledge of at least one of the implementation tools (Design Compiler or IC Compiler) and at least one of the verification tools (PrimeTime, Formality or VCS). Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete the workshop.
• Be aware of the basics of low-power design techniques. The workshop teaches you how to implement these techniques.

Unit-1: Synopsys Low Power Flow Overview

• Describe the input requirements for a UPF-based Low-Power flow
• Know the tools involved in accomplishing the Synopsys Low-Power Flow

• Correctly specify the multi-voltage libraries required in the low-power design flow
• Describe the functions of six special cells used in a multi-voltage design and identify the ones that are relevant during logic synthesis
• Write Top-Level and Hierarchical UPF specifications

• Query for power-intent information out of a synthesized design and correlate the findings with that of provided UPF file

• Describe how MVSIM verifies power states, transitions, and sequences
• Differentiate Electrically Protected (EP) vs. Accurate (EA) modes of MVSIM
• Perform MV-aware simulation using VCS and MVSIM

• Specify Power Domain and PVT requirements for MV optimizations
• State how each of the special cells (LS, ISO, ELS, RET) are synthesized
• Describe the UPF partitioning step during hierarchical synthesis flow
• Identify low-power synthesis scenarios for MCMM (LCA in 2008.09)
• Enable Power-domain and Voltage mixing during scan insertion
• List 2 techniques used by Low-Power ATPG to limit average power and peak power during scan testing

Unit-6: Functional, Power, and Timing Analysis (Lab)

• Logical Equivalence Checking
  • Equivalence checking RTL vs. Pre layout netlist using Formality
  • Signoff Equivalence checking using PG-connected netlist in Formality (Signoff step after P&R)
• Average and Peak Power Analysis
  • Perform Peak and average Power analysis using PTPX
  • Estimate pre-layout clock-tree power and power savings due to clock gating
  • Generate Peak power analysis data for IR drop analysis (Signoff step after P&R and parasitic extraction)
• Static Timing Analysis
  • Early Timing Analysis on the pre layout design netlist (using PrimeTime)
  • Signoff Timing Analysis based on the real voltage data at each cell obtained from PrimeRail (using PrimeTime SI -- Signoff step after P&R and parasitic extraction)
    

• Static Multi-Voltage rule checks using MVRC
• Describe what Architectural and Structural checks are done in MVRC
• Derive and check for safe sequences during the power up and power down
• PG checks (done during Signoff after P&R)
• Power-switch signal connectivity (done during Signoff after P&R)
  

Unit-8: MV Design and Power Grid Planning (Lab)

• Create, Shape, and Evaluate voltage areas
• Analyze and Synthesize Multi-Vdd power grids
• Make an exploration run to determine best power-switch cell array
• Place and pre-route power-switch cells
• Put all these steps together in a MVDD/MS (Multi-Vdd/Multi-Supply) flow
• Create a floorplan for MVDD/MS chips (Lab)

Unit-9: Implementation in IC Compiler (Lab)

• Placement
• Insert and Place Level Shifters
• Use a ScanDEF file for voltage-area aware DFT
• Use multiple libraries & multi-corner/multi-mode techniques during power optimization in ICC
• Use Instance-Based Targeting
• Perform VA aware High Fanout Net Synthesis
• Clock Tree Synthesis
  • Perform voltage-area aware CTS
  • Clock tree splitting and merging techniques
  • Advanced clustering algorithm
• Routing
  • Route Level-Shifter power
  • Route AON logic & buffers
• Signal Integrity
  • MV-aware

• Antenna fixes (VA-aware diode insertion)
• Spare Cell insertion
• Hold-time fixing
• Timing-Driven Metal Fill

• Rail analysis in Primerail
• Generating Power analysis scripts and invoking PrimeTime PX

• Design Compiler - Topographical
• DFT Compiler (with DFTMAX enabled)
• PowerCompiler
• Formality
• VCS
• MVSIM
• MVRC
• IC Compiler
• PrimeRail
• Star RCXT
• PrimeTime-SI
• PrimeTime-PX