Overview
The workshop teaches floorplan preparation for large, complex, integrated circuits. You will learn to partition a design into hierarchical sub-blocks for implementation in IC Compiler. All the Floorplan, constraint, and timing information required for implementation is created.

We begin with the creation of a Milkyway database and an initial floorplan. Next, standard cell and macro placement, using plangroups, guide the development of a physical hierarchy. Manipulation of the physical hierarchy is discussed in detail.

A discussion of the Jupiter Recommended Methodology and a new die-shrinking technology (MinChip) ease use of JupiterXT. 

We then demonstrate a number of methods for improving the quality of the Floorplan including: “Power Network Synthesis”, “Clock Tree Planning”, “In-Place “ and congestion-aware optimizations. Finally, we create soft macro blocks suitable for Place and Route processing.  Hands-on labs for all course units use a hierarchical design allowing exploration of all aspects of Virtual Flat floorplanning.

• Describe the JupiterXT Virtual Flat design
• Manipulate the hierarchy and create plangroups using the Hierarchy Browser
• Perform Power Planning using JupiterXT's Power Network Analysis and Synthesis capabilities
• Execute Virtual Flat Placement and refine the plangroups
• Perform automatic pin assignment on all blocks
• Generate HTV models for chip-level timing analysis and budgeting
• Define and develop effectivetime budgeting for Place &Route in Astro or IC Compiler
• Perform top level routing, physical timing optimization and timing analysis
• Generate your run scripts using Jupiter Recommended Methodology
• Take an existing design and compress it into a smaller footprint.

Audience Profile
Design or layout engineers with little to no experience with floorplanning using JupiterXT.

Prerequisites
There are no prerequisites for this workshop, other than basic knowledge of UNIX and ASIC design.

Course Outline

Day 1

• Introduction to Floorplanning with JupiterXT
• Die size reduction using MinChip
• Design and Timing Setup
• Virtual Flat Placement

• Power Planning and Synthesis
• Clock Tree Planning
• Preparing Blocks for Place & Route
• Jupiter Recommended Methodology

• JupiterXT 2007.03