Overview
This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design’s hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 4-page Job Aid which the student can refer to back at work..

• Create a setup file to specify the libraries that will be used
• Read in a hierarchical design
• Partition a design's hierarchy optimally for synthesis
• Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasitics
• Select the appropriate compile flow for your project
• Execute the recommended synthesis techniques within each compile flow to achieve area and timing closure
• Perform test-ready synthesis when appropriate
• Verify the logic equivalence of a synthesized netlist to that of an RTL design
• Write DC-Tcl scripts to constrain and compile designs
• Generate and interpret timing, constraints and other debugging reports
• Understand the effect that RTL coding style can have on synthesis results
• Generate output data (netlist, timing/area constraints, physical constraints scan-def) that works with downstream physical design or layout tools

Audience Profile
ASIC digital designers who are going to use Design Compiler to synthesize Verilog or VHDL RTL modules to generate gate-level netlists.

Prerequisites
To benefit the most from the material presented in this workshop, you should:

• Understand the functionality of digital sequential and combinational logic
• Have familiarity with UNIX and a UNIX text editor of your choice
• No prior Design Compiler knowledge or experience is needed

• Introduction to Synthesis
• Setting Up and Saving Designs
• Design and Library Objects
• Area and Timing Constraints

• Partitioning for Synthesis
• Environmental Attributes
• Compile Commands
• Timing Analysis
• More Constraint Considerations

• More Constraint Considerations
• Multi-Clock Designs
• Synthesis techniques and Flows
• Post-Synthesis Output Data
• Conclusion

• Design Compiler 2009.06-SP3
• Formality 2009.06-SP3