Astro 1
 

OVERVIEW

This workshop will enable the student to become proficient in using Astro to perform a timing-driven flow for placement, clock tree synthesis (CTS), routing and optimization to achieve timing closure for designs with moderate placement and routing challenges using a flat floorplan (chip or block). The main emphasis of the workshop is to learn a proven, effective flow that will achieve reasonable quality of results with fast time-to-market. The workshop covers the recommended flow steps for design set-up, floorplanning, timing set-up, placement, clock-tree synthesis, routing, optimization and design for manufacturability to achieve these results. Job aids will be provided to enable the student to recall and implement all the recommended steps back at the job.

This workshop will not cover advanced design closure features and flows such as: techniques of achieving timing closure on designs with complex or difficult placement, CTS and routing challenges, or signal integrity and power rail issues.

At the end of this workshop the student will be able to:

• Describe key concepts and steps associated with automatic place&route
• Verify that all input data and information required to use Astro is available
• Implement a floorplan including macros
• Configure Astro for a timing driven flow
• Perform placement, clock-tree synthesis, routing and optimization in Astro, achieving timing closure for designs with moderate placement, CTS and routing challenges, emphasizing fast time to market
• Verify quality of results by analyzing timing and skew reports, congestion maps and other reports
• Interface to Synthesis and sign-off STA tools

ASIC, back-end or layout design engineers with little or no experience in Apollo or Astro, who will be using Astro to perform automatic Place & Route.

No previous experience with Astro or Apollo needed. Previous experience with non-Synopsys automatic Place & Route tool is helpful, but also not required.

Day 1

Unit 1: Introduction to Place and Route

• Key concepts and steps associated with automatic place&route tools
  

• Reading in a design from Verilog
• Attaching reference libraries to the Milkyway design library
• Performing hierarchy preservation
• Loading SDC constraints
• Attaching TLU/TLU-Plus capacitance models
• Configuring the timing setup panel
• Performing a "timing sanity check"
  

• Handling scan chains (disconnect/reconnect, ScanDEF interface)
• Using AutoPlace to perform Pre-place, In-Place, and Post-Place optimizations
• Congestion analysis
• Critical range optimization
• Soft and hard blockages
  

• Applying clock tree exceptions (ignore/sync pins)
• Differentiating between global, local and useful skew
• Clock tree synthesis and optimization
• Post-CTS optimization
• Useful skew optimization
  

• Pad/Pin placement
• Power/ground grid creation
• Specifying the chip size and placement rows
• Macro placement
• Rectilinear block floorplanning

Unit 6: Recommended Astro Methodology (RAM)

• Setting up the RAM flow using the flow panel
• Customizing auto-generated command scripts
• Executing the RAM makefiles
• Flow customization (using Physical Compiler as an example)
  

• Power/ground routing
• Clock net routing
• Global routing
• Track assignment
• Detail routing
• Search and repair
• Post- and in-route optimization and CTO
  

• Antenna fixing
• Metal slotting and filling
• DRC/LVS checking
• Critical Area optimization
• Writing files for Static Timing Analysis sign-off

• Astro 2005.09
• PrimeTime 2005.06